Optimising Semiconductor Chip Placement with Machine Learning

Semiconductor chip placement is a critical step in chip design, but it is also a laborious task that can take up to weeks to complete.

FPGA (field-programmable gate array) and ASIC (application-specific integrated circuit) chips, which are widely used in consumer electronics and enterprise systems, can consist of hundreds to millions of transistors depending on their size and complexity. Before they can be manufactured, different modules have to be carefully arranged on the chip.

Given the complexity of today’s semiconductor products, this requires the expertise of highly-skilled and experienced engineers. When carrying out chip placement, the engineers work with rectangular grids, each of which contains parts of one or more modules. Poor chip placement can result in a product that does not meet performance specifications, leading to costly delays in production.

To address these challenges, chip design optimisation company Plunify decided to leverage artificial intelligence (AI) in its quest to help businesses and organisations build better semiconductor products.

Started in 2009 by two passionate engineers, Plunify seeks to improve design performance and save time and resources in the design process.

Working with AI Singapore under the 100 Experiments (100E) programme, it explored the use of machine learning to assist human experts and speed up the chip placement process. Computationally-efficient generative models were used to generate chip placements. Convolutional neural networks and other deep learning architectures were then applied to improve the quality of chip placement by predicting good placements for production.

The outcomes of the project were amazing. A ground-breaking 80 percent accuracy was achieved in applying image recognition to chip placement. This enabled Plunify’s chip design partners to slash the development cycle for products ranging from automotive power chips to 5G communications chips from 2 months to a week.

The prototyping cost for new chips was also reduced by 8 per cent, and new chip designs could be developed 10 times faster.

To find out more about our 100E Programme, please click here.

“The team from AISG provided much-needed expertise and diligence to help us design and craft the data pipeline and models for this effort. This was vital to the success of the project.”

Ng Harn Hua
Co-Founder of Plunify